The present invention relates generally to the field of computer processors and, more particularly, to migration of legacy software to a contemporary processor.
To remain competitive in the industry, semiconductor companies have continually evolved their processor architectures to take advantage of improved hardware and software technologies. Unfortunately, as processor architectures evolve, legacy software that has been designed for previous processor versions may not execute on contemporary processor designs. Moreover, the high-level source code for the legacy software may no longer exist or may not be available. As a result, it may not be possible to re-compile the legacy software for the new hardware architecture. Migration of legacy software to contemporary processors may, therefore, be a difficult proposition. Several conventional approaches to this problem will be discussed hereafter.
One approach to migrating legacy software to a contemporary processor architecture is to design the contemporary processor so that it may operate in one or more modes that are backward compatible with one or more legacy processors. The contemporary processor may effectively be viewed as a multi-processor system with only one processor enabled at a time. Additional constraints may be placed on the design of the register sets in the contemporary processor to ensure that the legacy software may reference the new registers.
Another approach to migrating legacy software to a contemporary processor architecture is to implement a hardware run-time translator that translates legacy software instructions into one or more contemporary processor instructions in real time as the code is fetched from memory. One drawback to this approach, however, is that the run-time translator may consume large amounts of silicon area and power to perform the code translation.
Still another approach to migrating legacy software to a contemporary processor architecture is to use a software program that analyzes the legacy software and translates the legacy software instructions into new instructions that are compatible with the contemporary processor architecture. Because great dissimilarities may exist between the legacy processor architecture and the contemporary processor architecture, the translated software may be inefficient in both execution time and memory usage. Software developers may re-write inefficient code segments; however, these revisions may be error prone and may also be time intensive.